Cyclone II-Exp.6


Okay, so I thought I might toddle through the whole set of examples anyway to bed down some things and to not get too ahead of myself and ta da!

Grrrr

Grrrr

 

Basically went from:

 

module KEY_NAND_LED ( A,B,F );

input A,B;
output F;
assign F =~(A & B);

endmodule

to:

module KEY_NAND_LED ( A,B,C,D,F );

input A,B,C,D;
output F;
assign F =~(A & B & C & D);

endmodule

You know the drill by now.  Restart, take a swig of your drink and plod on.

Don’t forget to update the pin assignment:

Which pins? Hmmm

Which pins? Hmmm

 

From your spreadsheet DEV-PIN:

K3 INPUT PIN_40
K4 INPUT PIN_45

So:

Almost there...

Almost there…

 

There we are:

Recompile for good measure.

Recompile for good measure.

Program the chip and

D30 OUTPUT PIN_65

Should be the LED lit and it will extinguish no matter which button or combination of buttons is pressed.

Now looking at the layout we see we are maxed out with our four inputs:

I wonder ...

I wonder …

So let’s add a 5th and see what happens.  I am just grabbing:

LCD_D0 INOUT PIN_53

No reason, I want to see the layout change – not so interested in running it on the board.

Of course!

Double grrrr!

Double grrrr!

Okay, so now two logic elements are being used.  Remember they cap inputs to four!

Notice new cell at top.

Notice new cell at top.

The bottom cell now looks like this:

Only two????

Only two????

The top cell has four inputs (like the original one).

Looking closer:

What's in a name?

What’s in a name?

In the red star is the “Sum Equation” for the gate.  It is “B & D”.  These are actually the input names for the data inputs to the logic element.  Notice in the red hexagon DATAB < F~0 and DATAD<E.  The “F” and the “E” relate to the output and one of the inputs of our modified verilog module.

Essentially, as the logic cells are capped at four inputs it has split the design into two logic elements, one with inputs A,B,C,D.  One is the output of A&B&C&D=F and the second is E&F~0=F (F~0 is just a clumsy way of having an intermediate result).

If you believe the RTL viewer it is:

Nice but not really true.

Nice but not really true.

In schematic speak its more likely:

and4&and2&or

and4&and2&or

 

Which matches, more or less, the technology map view:

Ah ha!

Ah ha!

So the coup de grace is the not gate is sitting on the output pin circuit, voila!

The final piece of the puzzle.

The final piece of the puzzle.

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