Cyclone II-Exp.7


Okay, so this one comes with some commented out code:

module SMG_LED (led_bit,dataout);

// input clk_50M ;
output [7:0] dataout;
output led_bit;

reg [7:0] dataout;
reg led_bit;

//always @ ( posedge clk_50M )

//begin

always led_bit <= ‘b0;

always dataout<=8’b11000000;

// end

endmodule

Nothing special here.  Code compiles and the number “9” lights up in a 7-segment LED.

Going to the pin assignments (open up the pin assignments now) you can see the allocation to:

LED_A OUTPUT PIN_93
LED_B OUTPUT PIN_92
LED_C OUTPUT PIN_87
LED_D OUTPUT PIN_86
LED_E OUTPUT PIN_55
LED_F OUTPUT PIN_58
LED_G OUTPUT PIN_79
LED_H OUTPUT PIN_113

Which are the 7-segments and the decimal place.

The other stray is:

LED_EN1 OUTPUT PIN_94

Which is why we’ve lit up the last 7-segment display on the right.

Change to:

LED_EN8 OUTPUT PIN_104

Recompile and voila!

First 7-segment LED on left should be lit up.

Change the line:

always led_bit <= ‘b0;

to:

always led_bit <= ‘b1;

and get:

 

Ignore this.

Ignore this.

What you actually get is you’ve turned off the 7-segment display.  That is nothing is lit.

That is the “EN” is, you guessed it, ENABLE and “0” is ENABLED and “1” is DISABLED.

 

All good.

 

Change the line:

always led_bit <= ‘b1;

back to:

always led_bit <= ‘b0;

 

Then change:

always dataout<=8’b11000000;

to:

always dataout<=8’b11000001;

 and get:

"Missing" segment.

“Missing” segment.

 

So, going from a 7-segment map, this is segment A:

ABCDEF G, no KY

ABCDEF G, no KY

Have a look at the pin allocation vs the pin map for the board:

Not 42 but 4*2+11

Not 42 but 42*2+9

LED_A PIN_93
LED_B PIN_92
LED_C PIN_87
LED_D PIN_86
LED_E PIN_55
LED_F PIN_58
LED_G PIN_79
LED_H PIN_113

 

Even better try:

always dataout<=8’b01111111;

and get:

D D D D Decimal place!

D D D D Decimal place!

Without point too fine a point on it, of all the LED_x …

LED_H OUTPUT PIN_113

… is the decimal place yes!

Remember, we set the enable to first 7-segment LED with:

LED_EN8 OUTPUT PIN_104

Try different values, just walk through B, C, D, etc.

//Commented out code

So, the code that is commented out.

Play around with it to get it to work.  Answer is here.

Now for this to work you have to assign another pin.  The pin name in the code helps as it refers to a pin in the DEV-PIN spreadsheet, namely:

CLK_50M INPUT PIN_17

 

Compile and run it and …

… “9” appears on right (if we start with original code and simply un-comment lines).

So, assuming we have a 50 megahertz signal (50M) running internally, driving the enable we are very likely not to see any flickering etc. that you might expect with a much slower clocking of the enable.  Which gives a hint that if we want to see blinking, we might need to divide down the 50M clock input somewhat.

Not this time around.  Look on the interwebything.  There will be Verilog code examples for dividing circuits.

Advertisements

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: