Archive for July, 2014

Anti-Maker Sentiment

Posted in Anti-Maker Sentiment on July 29, 2014 by asteriondaedalus

New Category.

Anti Maker Sentiment.

Nothing nasty but Maker community I used to think was just Electronic hobbiests with a new communication medium of the internet.

However, the electronic hobbiests are often the ones designing the modules and gadgets and the Makers are really Assemblers.

A bit like the confusion many people have nowadays when they say “I built a computer on the weekend” … meaning they bough cards and cases and assembled things.

Not a bad thing mind you but I got excited and bought modules and joined them and found it a hollow victory all up.

So, back to building from scratch, which is the why of the DSP saga and the why of the FPGA saga et cetera.

How hard is it to program a eeprom?

Posted in cheap obsolete tech, Development, DSP, DSP Laboratory, Hardware on July 29, 2014 by asteriondaedalus

Pretty tricky if it is obsolete so no programmers around for it.

The AT17C65 is the eeprom configurator used in the eval board that the ADMCF328 sits on.

You can probably see where I picked up the fidgety RS232 approach with the AD chip and the optocouplers.

Now I know what you are thinking.  Swap it out for another chip.

Kooky idea.

Except the of the three chips that the ADMCF328 are design to work with (XC17165E, AT17C65, or 37LV65) the AT17C65 is the only one I can readily find on the aftermarket in China.  Absolutely no programmers for it though (although ATMEL have a tease page for a programmer but you can’t get it anymore, and why would you as the chip isn’t stocked anymore).

Thank you Mouser for one idea of how to build a programmer.

Although clincher came from ATMEL site along with the software for the configurator.  So, since the software seems to install on my Windoze box, I just need a DB25 parallel port – yes I said a DB25 parallel port.

Now, this goes either of two ways.  First is a USB to DB25 cable and driver, hopefully the configuration software recognises that arrangement.  Total cost $1.98.

Failing that, $6 to $11 dollars for a PCI card with DB25 parallel port and the ATMEL configurator software.

Failing that, ATMEL has also provided AVR code for programming AT17C65 so I would just code something up on my Arduino MEGA1250.

Okay, so either of 3 ways, 4 if you count no can do – which we don’t do we!

Why all this trouble?

Later chips work slightly differently and there is no guarantee the ADMCF328 will read other chip types.  Since getting a flashing LED on this little DSP chip will be proof I can program it having the right eeprom makes sense to avoid compounding the problem.

Although, the first flashing LED experiment will be against serial port boot.

Stay tuned.

PS, no Maker get out clause no way no how … I like it.


Ah ha! moment

Posted in Android, Python RULES! on July 23, 2014 by asteriondaedalus

I am having a problem with python libraries in QPython as I found that libraries seem to be visible to the script menu but not to the console.  The libraries were not turning up where I was expecting so I poked around using AndroZip which has a search function.

I worked out that, as I hadn’t put SD cards into any of my newer Android devices, the libraries were going into a cache that essentially was pretending to be the SD card.  For whatever reason, only the script menu could see the libraries at that location.  The QPython team promise they will look into fixing that but there is no reason for me not to bulk out my devices with SD cards.

I’ll buy a swag of SD cards this weekend and try uninstalling and then re-installing everything.

Got there

Posted in DSP, DSP Laboratory, Hardware on July 23, 2014 by asteriondaedalus

So, a little birds nesting and a lot of fiddling convinced me from moving away from the AD chip with opto-couplers.  So, I went for a MAX232 after all, with benefits.


Why not?

So the setup for the ADMC32x is now:

More sensible

More sensible

The other side is this module is more useful as I can use it on other experiments.  The other way was too sensitive to bumps and knocks and I need a “quiet” interface because the problem is working out whether I am getting code onto the chip – and not whether my birds nested serial interface is up or not.

10MHz clock is still coming from MAX CPLD.

Python Agents, SPADE and QPython

Posted in Android, Open Source can be professional, Python RULES! on July 13, 2014 by asteriondaedalus
Gotta love open source ... sometimes

Gotta love open source … sometimes

So, I pulled together PyDev and a mystical FTP plugin (from general tools under Indego) to get access to my Android devices when writing QPython code.  I tried a couple of FTP servers on Android (including the neat FTP server that comes with QPython) but there was a road block.

The default port for FTP appears to be 21 and the Eclipse FTP plugin doesn’t let you change this.

The FTP server built into QPython will let you set the port to 21 (it defaults to 2121) but it won’t start.  Android won’t let you run ports below a certain level without root permission.

A couple of other FTP servers I downloaded had the same problem until I came across FTPDroid which allows use of port 21 if you have root access – which comes with by JXD S7800B and I have also rooted my old Galaxy Samsung SII, so all good.

Additionally, I had a little problem (sorted by QPython authors) with missing modules that stopped installing SPADE into QPython but that all appears good as I had a couple of agents running on the JXD S7800B with the server on my PC.  So, code above is me hacking SPADE agents on an Android device running QPython.


Posted in Cyclone II Experiments, FPGA on July 8, 2014 by asteriondaedalus

Okay, so I set myself a task to discover why I was getting ghosting in the display for Part VI of LAB 1.

The black and white box shows the ghost “A”.




This would be that the segment signals were not changing until after the display enable – carrying over the previous character for a short time before the blank is drawn.

Now this, in the un-registered approach, is plausible.  It means the signal paths for the segment drivers are longer (somewhat) than the display enables.

Bugger is, to date, I have failed to get a registered version working.

Of note, I used Fizzim to create a Verilog and a VHDL state machine to try driving the displays to find the same state machine input gives a Verilog soluton that generates rubbish (despite reading as if it should work); and a VHDL version that currently doesn’t clock, and so just shows the second character but reacts nicely to button input.

So, I decided to fire up ModelSim, which comes with Quartus, to see if the simulator would spread any light on the subject.  That will take a little time to sort out as the simulated version of the code that works (but ghosts) never seems to generate outputs, though I can step through the sweep generator fine.

I may get lazy and just use my LogicSniffer for the moment – at least to test the theory of the lag between the segment and display enables.

Fingers crossed.

I will put together the whole story once I have worked it out.