VHDL DIGITAL LOGIC LAB 2


I’ve been bad.

So stay tuned, LAB 2 will be teased out as a study break during my Dissertation.

Update

I dumped Part I of LAB 2 onto the FPGA board and DOH!

There was a little twiddling to read the design across from the Altera boards to the MASTER 21EDA.

What I forgot was the switch logic is tied high and goes low when you press the switch.  So, no big problem really but since I am writing it up for followers I had to revisit the LogicFriday defined equations to flip the logic table.  The software has an invert function which has helped a couple of times BUT it inverts rows and does not flip tables.

Anyway, a little work to re-code the work and then it will start going up – as usual – one Part of the lab at a time.

Don’t hold your breath though – Dissertation started so will be infrequent for next 20 odd weeks.

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