Archive for September, 2015

j1 – almost

Posted in FORTH is it dead or isn't it?, FPGA on September 16, 2015 by asteriondaedalus

A while back I had a poke at porting the J1 FORTH softcore to Altera.

Yep, ahead of my meanderings with the Altera LABS but I have spent years in software development and real-time DSP and other systems so the LABS are just me being methodical and giving back to the community.  My main aim, eventually, is DSP and vision experiments.

Not being a slouch I then speed off to at least play at a larger level of granularity and so the FORTH softcores.

Any old how, J1 did allude me because it is coded for XILINX and had some pesky RAM code definition that did not come with the J1.  Ended up finding the XILINX code for the RAM and so I have got most of the way through the porting.  Just some pesky problems with Altera version of Verilog not covering the same expanse of the spec as the XILINX compiler.

All good, as it is all a learning vehicle.

Stay tuned then.

Sneaky nasty Windoze 10

Posted in Uncategorized on September 15, 2015 by asteriondaedalus

Watch out!  I have CHROME installed on Windoze 10. I have CHROME set as my default browser.  Occasionally webpages pop up and tell me my browser is out of date.  Thing is the webpages are telling me they are detecting IE and not CHROME.

Might be a problem with the web page yes?

But it is IEEE webpage telling me it sees IE on my machine and not CHROME which is what I am running to look a the IEEE web page.  What sneaky nasty game are MICROSOFT playing?

Stop me

Posted in Altera Labs, FPGA, fpga MAX10 on September 9, 2015 by asteriondaedalus

God. I am like a little kid. Turned 56, my parents sent me a check. I hid it from the wife and bought myself a BeMicro MAX 10 board.

uCore on BeMicro

So, first thing was not “hello world”, rather I jammed on the uCore FORTH CPU to see if it would fit.  It seems to have more room than on my EP2C8Q208C8N board!  Whats more it is the configuration I am after for a general purpose FORTH board.

Now, options include getting uCore up and running with Avalon bus connectivity.  The other option is very sentimental.  I have the bin dump for RSC Forth for the 65F11/12 which is essentially 6502 with extras.  Might be fun to get that going on the board as an exercise.

Of note however:

Die Seite steht zur Zeit nicht zur Verfuegung

That is the uCore website is not available.  Interesting, the shortcoming of uCore seemed to be the licence arrangement.  Now if the site is down what does that mean for the licence.  The issue with the licence is that it limits commercial use – so what if you’ve no commercial intent.  However, begs the question.  If the site is down because the owner’s interest has waned then how much of that has been influenced by the licence turning people away.  It is a FORTH implementation after all, which is a niche market likely of people, like myself, with some sentimental attachment only.   Why have commercial limitations then on an unproven implementation in a sphere not widely trodden?

Windoze 10 – Thank god for desktop icons and for taskbar

Posted in Windoze10 on September 1, 2015 by asteriondaedalus

Well, Windoze 10 is officially fracked up.

I went to install Altera Quartus II rev 15 and nope nothing, nix, nadda went into the so-called “All apps”.  So I am running it from a desktop icon.  That has dissuaded me from ripping out rev 11.1 and re-installing (I am still queasy about keeping what I have set up for my Cyclone II boards but I need rev 15 for the MAX 10 board I ordered).  I assumed I could clean up the half constructed rev 11.1 folders in the “Stop Menu” but nope, not going to play.

Looking forward to Windoze 11 (*** reaching for the razor blade ***).

Part IV of Lab 2

Posted in Altera Labs, Cyclone II Experiments, FPGA on September 1, 2015 by asteriondaedalus

Here is were I am up to with Digital Lab 2, having sorted out what I thought was an issue with Part IV.  Turns out I opted to invert inputs into the seven segment display code of an earlier part, but had to re-code for un-inverted inputs.