Archive for March, 2016

Gag!

Posted in Sucky service Providers on March 30, 2016 by asteriondaedalus

Got a new router from Telstra the other week.  Didn’t pop it online until tonight because Telstra shut down the service to the old router … so wifey she screamy loud.

I had high hopes BUT …

… I may have bleed my bleeding heart over these pages about the problems I have had with my WIFI since I downgraded my PC from Windoze 7 to Windoze 10.

Same old same old.

I wasn’t surprised when my box did not see the 5G connection.  I was secretly expecting thought that I could hop back onto the 3G connection.  As I have been piggy backed off a wireless extender for 6 months, I was expecting that the wankers at Microsoft had sorted WIFI problems.

Nope.

Here I am piggy backed off my wireless extender.  Nope it doesn’t see the 5G either.

No biggy.

Enough to get by.  I will think about getting a new WIFI board as soon as I can trust that Microsoft has … no … I will keep my money.

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Super Dooper Computer

Posted in ODROID is wonderful on March 25, 2016 by asteriondaedalus

All things come to those who wait.

Two mates came to party with free gifts.

One gave me a large stylish server case so I can build a old dual core server mother board into.  I am sourcing a CUDA board to get best GPU-bang for buck to build a OpenCV/PCL server to give some of my smaller roving bots a vision and mapping service.

To boot, another mate gave me his ODROID C1 so I now have a 4 board ODROiD C1 cluster!

This is for some of the experiments with ERLANG/ELIXIR/RIAK/Phoenix I am dabbling with.  Not to mention RabbitMQ et al.

I have been playing with RabbitMQ and emqtt to sort communication across network with ESP8266 and the 4 ODROID-W skattered around the place.  Currently running emqtt and node-red on an ODROID-W mounted on baseboard but once I have sorted things I will move it to a headerless ODROID-W to sit humming hidden in a small box out of site.

All good fun.

OM I say OMG!

Posted in ODROID vs RaspingBreathburry on March 22, 2016 by asteriondaedalus

IMG_4090-500x334

RaspberryDoodleDandyPoodle :- 64bit, 4 core, 1.2GHz, 1Gbyte memory, AUS$70!  Just the thing for a 12 year old bored skool kid to fry.

ODROID-C2

Odroid C2 :- 64bit, 4 core, 2GHz, 2GByte memory, AUS$70!

The built in bluetooth and wifi on the RaspberryDoodleDandy … hmmm … not enough.

Even the Odroid C0 makes more sense than the Raspberry OH NO!  Unless you want to turn on an LED whenever the local cocker spaniel cocks his spaniel on you mailbox … nope not even then, got a drawer full of ESP8266 for that.

Don’t buy this

Posted in cheap obsolete tech on March 12, 2016 by asteriondaedalus

Junk

Owner of shop does not help with setup files and some people note damaged articles.

God I am so rusty with my math

Posted in Altera Labs, Cyclone II Experiments on March 8, 2016 by asteriondaedalus

Not to mention the twists when doing math in VHDL.

Okay, I will mention it.

So dusting off the FPGA Labs from Altera University pack, recall we are working through Digitial Lab 2, in VHDL, to port it from DE0 or DE1 to  MASTER 21EDA BASIC CYCLONE II EXPERIMENTER’S BOARD!

I am currently up to Part V of Digital LAB 2 … what? … lay off!  I have been distracted somewhat … get over it.

Any old how, the math thing.

Here is the problem.

fpga math

The deal is that previously we were building a bcd adder by the numbers, using logic.  Now we are to build it algorithmically.  It is, however, more or less what the logic did.

Can’t be hard right.  Just like programming.  BUT it isn’t. Remember we are predominantly defining and wiring blocks of logic together.  In places, many many  places, we get what you might call in programming terms “concurrency” or “parallelism” because once things are wired together they can and will all send signals simultaneously if the layout permits.  All part of the problem of building logic circuits in VHDL or in Verilog.

The other thing is, being as we are building logic circuits, bits and vectors of bits rule Man!

So, it took a little work because we needed, firstly, to read into casting.  Some quirks came out, of course.

Short cut is the following VHDL code.  It compiles but I am still to debug so don’t get too excited.  However, worth taking a pause.

fpga math2

So a few things first.  Many authors of *cough* VHDL help will likely baulk.  There are some fashionable rules about how NOT to use STD_LOGIC_VECTOR, and adding is one of them.  The mantra is it’s for bits and other “types” are for math.  Never mind we also have a STD_LOGIC type in the carry flags!  (Well, we’ll mind don’t you worry about that.)

The thing though, we are learning and this brings out useful nuances to get your head around.  It did take a little time to click as one did have to read things once or twice … or thrice.

The other side, I am trying to get re-use out of the infrastructure already built in earlier parts of the lab so the inputs out outputs are STD_LOGIC_VECTOR and STD_LOGIC … so there.

The types for a_in, b_in and c_in are:

a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;

One thing to note, in all the scribbling out there, is that signed and unsigned are vectors so they can be cast to/from STD_LOGIC_VECTOR.  A good explanation is at bitweenie.

So, end result is that the following worked:

t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in));

The following did not work:

t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in) + unsigned(c_in));

Similarly the following did not work:

t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in) + c_in);

It took some head scratching but the line that worked was:

t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in) + (c_in & ""));

The gem, of course, was the (c_in & “”).  The ampersand or & is a concatenation operator in VHDL.  So, you are building a vector of one or, say {c_in} as opposed to c_in.  That is the “” is an empty vector so an empty vector plus an entry is a non-empty vector of one entry.  Think of vector then as array.  A good explanation, with examples, is on page 41 of a tutorial on VHDL by Peter Ashenden.

 The line I am dubious about is:

s_out <= STD_LOGIC_VECTOR(unsigned(t) - unsigned(z));

I actually curious whether I need to use signed instead, so a little thinking still to do.

Not to mention the idea that if I make z (4 DOWNTO 0), instead of (3 DOWNTO 0), I naturally get a carry bit without having to have the extra signal and so I likely can do something like this:

c_out <= z[4];

Meaning I can get rid of some of the intermediate signals.  We’ll see.

Still poking around.

Oh yeah.  It is in a process block because it has to be sequential, like a program, and not a bunch of wired up logic.  That is that other twist you need to remember.

It never rains …

Posted in Doodling on March 3, 2016 by asteriondaedalus

… it is pouring conference papers.

I have just had two more papers accepted at another conference so hobby things back on hold.

Still might do some more work on crawler this weekend while watching a movie.