Archive for the FORTH is it dead or isn’t it? Category

It’s all a matter of timing

Posted in Chapel, Elixir, Erlang, FORTH is it dead or isn't it?, Parallella on June 24, 2017 by asteriondaedalus

So, phew!

I re-bombed parabuntu onto the SD card.

What the problem was earlier was the security key had changed but I was forgetting to say YES to option for saving the new key (I had quite a lot of red wine last night so don’t be so hard on me ūüėČ )

When I powered up the Parallella again, I wasted no time and jumped in with:

sudo nano /etc/network/interfaces.d/eth0

---- inside of nano ---

auto eth0
iface eth0 inet static
address // your parallella IP here
netmask // your netmask here
gateway // your gateway address here
dns-nameservers x.x.x.x //your dns server list here

--- exit and save ---

sudo reboot

Happily now running on the static IP set … phew!

Now to work.

Target environments will be erlang/elixir and chapel.  Yet, ePython for poking around.

I am reading back into my threaded interpretive days to look at a minimal FORTH runtime to run on the Epiphany. ¬†There has been chatter on the parallella groups about J1, but that is a HDL (read FPGA) FORTH. ¬†I think many people chattering haven’t worked in FORTH so much of the chatter is unproductive. ¬†I am thinking a GForth running on the ARM side that assembles, rather than cross compiles, to a hand built threaded interpreter on the matrix. ¬†I am not sure how feasible that all is but it will be ¬†a good instrument for learning the nuts’n’bolts of Epiphany.

Many lessons can come from the struggle, yes?

This, idea is no more or less I worked on during a project, in Canada, where I noted the DSP software the team was using was already using a threaded processing chain.  The idea then of control loops and conditional inside of that was a soft sell.

So, in FORTHeze no outer interpreter running on the Epiphany.


Why priori knowledge is so irritating

Posted in Factor programming language, FORTH is it dead or isn't it? on May 20, 2017 by asteriondaedalus

Something so simple, if you have example code on your blog why on earth do you not included the includes.  Priori knowledge is not immediately explicit.

I bumbled through the example of constraint based programming in Factor.  Go figure, the actual code should be:

USE: backtrack
USE: locals

:: solve-711 ( -- seq )
    711 iota amb-lazy :> w
    711 w - iota amb-lazy :> x
    711 w - x - iota amb-lazy :> y
    711 w - x - y - :> z

    w x * y * z * 711,000,000 = [ fail ] unless

    { w x y z } ;

Run it with:

IN: scratchpad solve-711 .

Still, the debugging is fantastic and will suggest vocabularies to include (which helped sort out the missing “includes” aka USE:).

Interestingly Factor has a vocab “models” which sniffs a bit like the idea of models, in the first instance from MVC, but then subtly not unlike the way “model” is used in Elm¬†and therefore¬†Functional Reactive Programming. ¬†Cool.

Although, its¬†Concatenative Reactive Programming really – although that’s postfix functions rather than prefix. ¬†Cool.

The difference is important though. ¬†Elm “compiles” to JSP to “compile” to byte-code to run on the JVM. ¬†In Factor, you are reactive in Factor.

Now, the key difference between Factor and Forth here is that Forth is for embedded systems. ¬†Factor is not. ¬†While you can squeeze Forth onto an AVR chip, they don’t even bother anymore with Factor on ARM.

Still, I get a queasy feeling it’s the FORTH community all over again.


Posted in FORTH is it dead or isn't it? on January 24, 2017 by asteriondaedalus

Factor is to FORTH what my Subaru Impreza WRX is to my Alfa Sud.

I didn’t even know I was looking for it.

j1 – almost

Posted in FORTH is it dead or isn't it?, FPGA on September 16, 2015 by asteriondaedalus

A while back I had a poke at porting the J1 FORTH softcore to Altera.

Yep, ahead of my meanderings with the Altera LABS but I have spent years in software development and real-time DSP and other systems so the LABS are just me being methodical and giving back to the community.  My main aim, eventually, is DSP and vision experiments.

Not being a slouch I then speed off to at least play at a larger level of granularity and so the FORTH softcores.

Any old how, J1 did allude me because it is coded for XILINX and had some pesky RAM code definition that did not come with the J1.  Ended up finding the XILINX code for the RAM and so I have got most of the way through the porting.  Just some pesky problems with Altera version of Verilog not covering the same expanse of the spec as the XILINX compiler.

All good, as it is all a learning vehicle.

Stay tuned then.

Here’s the thing

Posted in Cyclone II Experiments, FORTH is it dead or isn't it? on September 17, 2014 by asteriondaedalus

Forth in hardware on FPGA!

So, of all the options found uCore seems best as it compiles on my EP2C5T144C8, voila!:

Oh so squeezy!

Oh so squeezy!

So only just.

However, this board has no RAM et al so not a lot of point (since you need external RAM and ROM (so-called).

However, on my bigger Altera Cyclone II board it has room to spare (a little) and RAM et al on the board (no ROM but I will have to sort that some old how).  Here is the map:

A tad more room!

A tad more room!

There is a config file (more or less, a constants file) that allows you to tune the CPU so I will look at what that might do for me.  However, first thing will be to sort out a blinking light app.


Posted in FORTH is it dead or isn't it?, FPGA on May 3, 2014 by asteriondaedalus

So, study over and I was wondering …

So, the HIVE code sucks up into Quartus 10.1 fine (it appears to have been written for 9.x).

The problem … needs a bigger FPGA chip than our¬†EP2C5T144C8 chip. ¬†I have a board with¬†EP2C8T208C8 coming but, alas that is too small too (there are no¬†EP2C70xxxxx boards on Aliexpress in any event).

Looks like you have to invest in Cyclone III and above.  Not an option at the moment till we spend about 12 months learning the art of FPGA I think.

I have a Mojo board with a Xilinx Spartan 6 on board so I jump onto my Xilinx tools (which I haven’t used yet ūüėČ ) and loaded up J1 and dang thing wouldn’t build so that will need some work – I guess its a good way to learn the environment. ¬†Oddly, it seems to come up in the simulator so it seems to compile fine, just fails layout.

Pretend J1

Pretend J1

So, I might spend a little time with the simulator manual and pour over the model every now and then to work out the tool and check out the cpu that way.


Arduino on Steroids!

Posted in Arduino, FORTH is it dead or isn't it?, FPGA on April 29, 2014 by asteriondaedalus

What can I say?

I put my name down for funding it at INDIEGOGO.

The project brilliant.  Done to an Arduino IDE mod to do multi-threaded work.

It is up there with XMOS and Parallax Propeller.

Now, I wonder … you could probably use this technique to have a multi-threaded FORTH engine. ¬†Not as many “cores” as Chuck Moore’s¬†G144A12 Chip but likely more practicable given not every one will need 144 cores for practical projects.

I guess optional cores are:

  • J1¬†and as implemented on the gameduino¬†(XILINX).
  • myforthprocessor at OpenCores – really BIG and comes with compiler. ¬†Core includes floating point and it appears already has multi-core option (Xilinx).
  • HIVE at OpenCores – already has 8 threads (Altera but needs a bigger chip than on our experimenters board).

Certainly, as far as the cloudx project is concerned, there may be impetus for a cut down version that could be used (4 AVR MCU/threads say) without as much companion real estate as a APM-Multithread.  Just saying.


Dead project. ¬†Chap couldn’t get the backing. ¬†Oh well.