Archive for the FPGA Category

j1 – almost

Posted in FORTH is it dead or isn't it?, FPGA on September 16, 2015 by asteriondaedalus

A while back I had a poke at porting the J1 FORTH softcore to Altera.

Yep, ahead of my meanderings with the Altera LABS but I have spent years in software development and real-time DSP and other systems so the LABS are just me being methodical and giving back to the community.  My main aim, eventually, is DSP and vision experiments.

Not being a slouch I then speed off to at least play at a larger level of granularity and so the FORTH softcores.

Any old how, J1 did allude me because it is coded for XILINX and had some pesky RAM code definition that did not come with the J1.  Ended up finding the XILINX code for the RAM and so I have got most of the way through the porting.  Just some pesky problems with Altera version of Verilog not covering the same expanse of the spec as the XILINX compiler.

All good, as it is all a learning vehicle.

Stay tuned then.

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Stop me

Posted in Altera Labs, FPGA, fpga MAX10 on September 9, 2015 by asteriondaedalus

God. I am like a little kid. Turned 56, my parents sent me a check. I hid it from the wife and bought myself a BeMicro MAX 10 board.

uCore on BeMicro

So, first thing was not “hello world”, rather I jammed on the uCore FORTH CPU to see if it would fit.  It seems to have more room than on my EP2C8Q208C8N board!  Whats more it is the configuration I am after for a general purpose FORTH board.

Now, options include getting uCore up and running with Avalon bus connectivity.  The other option is very sentimental.  I have the bin dump for RSC Forth for the 65F11/12 which is essentially 6502 with extras.  Might be fun to get that going on the board as an exercise.

Of note however:

Die Seite steht zur Zeit nicht zur Verfuegung

That is the uCore website is not available.  Interesting, the shortcoming of uCore seemed to be the licence arrangement.  Now if the site is down what does that mean for the licence.  The issue with the licence is that it limits commercial use – so what if you’ve no commercial intent.  However, begs the question.  If the site is down because the owner’s interest has waned then how much of that has been influenced by the licence turning people away.  It is a FORTH implementation after all, which is a niche market likely of people, like myself, with some sentimental attachment only.   Why have commercial limitations then on an unproven implementation in a sphere not widely trodden?

Part IV of Lab 2

Posted in Altera Labs, Cyclone II Experiments, FPGA on September 1, 2015 by asteriondaedalus

Here is were I am up to with Digital Lab 2, having sorted out what I thought was an issue with Part IV.  Turns out I opted to invert inputs into the seven segment display code of an earlier part, but had to re-code for un-inverted inputs.

DL-L2

Part III of Lab 2

Posted in Altera Labs, Cyclone II Experiments, FPGA on August 29, 2015 by asteriondaedalus

Here is were I am up to with Digital Lab 2, having sorted out what I thought was an issue with Part III.  Turned out I was muddled by my use of 4 bit LPM constants so I just opted for 4×1-bit constants so as not to confound.

DL-L2

Hmmmmm

Posted in Altera Labs, Cyclone II Experiments, FPGA on August 20, 2015 by asteriondaedalus

When testing Part III of Lab 2 there were some anomalies. Here is where I am at – DL-L2.

I have double checked the 1-bit adder so I am thinking it is in the wiring up.  I think also I have forgotten, as usual, that the input pins need inversion before use (since they are pulled UP).  Still, when I pulled them up, I still got weird results so that points back to the wiring up.

Stay tuned for corrections.

VHDL DIGITAL LOGIC LAB 2 Interim

Posted in Altera Labs, Cyclone II Experiments, FPGA on July 12, 2015 by asteriondaedalus

LAB 2 in work, here are parts 1 and 2 at DL-L2.

No such thing as a Ghost

Posted in Altera Labs, Cyclone II Experiments, FPGA on July 12, 2015 by asteriondaedalus

Well, not anymore.

You may or may not recall during the LAB I work that we knocked up a module to allow our Master 21EDA board to behave somewhat like a Altera DE1 board with respect to the way the displays worked.

While the original code worked it had a bug where a ghost of the preceding digit would show on the current digit display.

The problem was sorted thus:

no ghost

Now it turns out if the signal M is 2bit then this doesn’t work.  There is still a hangover were the enable moves to the next digit before the digit value changes.  The fix was then to set M to a 3bit counter and then set the unused cycles to all ‘1’ – so all blank led segments when HEX=”1111111″, and setting all display enables to disabled when DISPn=”1111″.

NOTE

This is still clunky.  It may be fine for the display problem but it is likely not the best for signal problems (there may still be glitches in timing but the LED isn’t bright enough now to notice).  Will need some investigation still and some playing with registering via coding patterns.  The likely way we want to fix it properly is to set the enables high, select the digit, then set the enable low each time.