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Setting up ModelSim with Quartus II … how hard can it be?


Starting with the “Getting Started with Quartus II Simulation Using the ModelSim-Altera Software” get straight into trouble.

You need a “counter.zip” file that is, you guessed it, not in the distro.

Various “counter.zip” files appear an Altera site and, of course, there are about 1 billion trillion of them on the interwebby thing all up.

Seems the one needed has a “counter.qpf” inside of it … have you seen it?  Hmmm?

So I went back to Altera and downloaded a raft of docco for 10.1.

I don’t know … I don’t get the feeling you get the same bang for buck this way Xilinx as you do for Altera.

In any event, I feel another laboratory report coming on.

 

This entry was posted on May 9, 2014 at 2:50 am and is filed under The Downside of software development. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.

2 Responses to “Setting up ModelSim with Quartus II … how hard can it be?”

  1. asteriondaedalus Says:
    December 19, 2014 at 5:40 am

    PS, don’t worry about the output signals “result”. For the exercise they will simply output the count as signals in the simulator.

  2. asteriondaedalus Says:
    December 19, 2014 at 5:38 am

    Yeah. I just used the file at:
    http://www.altera.com/support/examples/verilog/ver-counter.html

    It is a verilog file only. Just create a project called counter with a top level component called counter. Suck this file in. Make it the top element to be sure to be sure. It has an enable input so either set the enable high in the simulator OR create a project etc. and type in:
    module counter
    (
    clk,
    reset,
    result
    );

    input clk;
    input reset;
    output [7:0] result;

    reg [7:0] result;

    always @(posedge clk or posedge reset)
    begin
    if (reset)
    result = 0;
    else result = result + 1;
    end
    endmodule

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